Referenced Items are not available for this document.
A novel planar accumulation channel SiC MOSFET structure is reported in this paper. The problems of gate oxide rupture and poor channel conductance previously reported in SiC UMOSFETs are solved by using a buried P/sup +/ layer to shield the channel region. The fabricated 6H-SiC unterminated devices had a blocking voltage of 350 V with a specific on-resistance of 18 m/spl Omega/.cm/sup 2/ at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 2.5/spl times/ of the value calculated for the epitaxial drift region (10/sup 16/ cm/sup -3/, 10 /spl mu/m), which is capable of supporting 1500 V.
Published in:
Electron Device Letters, IEEE
(Volume:18
,
Issue:
12
)
Date of Publication: Dec. 1997
- Page(s):
- 589 - 591
- ISSN :
- 0741-3106
- INSPEC Accession Number:
- 5783691
- Digital Object Identifier :
- 10.1109/55.644080
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Dec. 1997
- Sponsored by :
- IEEE Electron Devices Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
