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Investigation of interface traps in LDD pMOST's by the DCIV method

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6 Author(s)
Jie, B.B. ; Fac. of Eng., Nat. Univ. of Singapore, Singapore ; Li, M.-F. ; Lou, C.L. ; Chim, W.K.
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Interface traps in submicron buried-channel LDD pMOSTs, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOSTs. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high.

Published in:

Electron Device Letters, IEEE  (Volume:18 ,  Issue: 12 )