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An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm

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2 Author(s)
Jah-Ming Hsu ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chin-Liang Wang

Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurring in the transmission process. Since the decoding process for RS codes is rather computation-extensive, special-purpose hardware structures are often necessary for it to meet the real-time requirements. In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for RS decoding. The architecture is developed based on a time domain algorithm using the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder can process one data block every n clock cycles, i.e., the average decoding rate is one symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency

Published in:

Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:7 ,  Issue: 6 )

Date of Publication:

Dec 1997

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