By Topic

ProTest: a low cost rapid prototyping and test system for ASICs and FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Jacomet, M. ; Biel Sch. of Eng., MicroLab, Biel, Switzerland ; Walti, R. ; Winzenried, L. ; Perez, J.
more authors

The test bench methodology helps the design engineer to structure the simulation of his circuit. As showed in this paper, the test bench methodology can further be developed in order to efficiently reuse simulation stimuli and response for the real device under test. As FPGAs are very often used to prototype an ASIC design, an easy switch between simulation and real hardware test is necessary to establish a rapid prototyping design and test environment. Our ProTest system closes the gap between the simulation and the test environment with a low cast and easy to use computer-aided-test environment

Published in:

Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian

Date of Conference:

17-19 Nov 1997