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Interconnect layout optimization under higher-order RLC model

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2 Author(s)
Cong, J. ; Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA ; Cheng-Kok Koh

Studies the interconnect layout optimization problem under a higher-order RLC model to optimize not just the delay but also the waveform for RLC circuits with non-monotone signal response. We propose a unified approach that considers topology optimization, wire-sizing optimization and waveform optimization simultaneously. Our algorithm considers a large class of routing topologies, ranging from shortest-path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required-arrival-time Steiner (RATS) trees, providing a smooth trade-off among signal delay, waveform and routing area. Using a new incremental moment computation algorithm, we interleave topology construction with moment computation to facilitate accurate delay calculation and evaluation of waveform quality. Experimental results show that our algorithm is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot and routing cost.

Published in:

Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on

Date of Conference:

9-13 Nov. 1997