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Verifying correct pipeline implementation for microprocessors

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2 Author(s)
J. Levitt ; Comput. Syst. Lab., Stanford Univ., CA, USA ; K. Olukotun

We introduce a general, automatic verification technique for pipelined designs. The technique is based on a scalable, formal methodology for analysing pipelines. The key advantages to our technique are: it specifically targets pipeline control, making it more efficient; it requires no explicit specification, since it compares hardware against itself; it can be used within the broader framework of hierarchical verification; and, it can be easily extended to handle certain "complex" pipelined structures.

Published in:

Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on

Date of Conference:

9-13 Nov. 1997