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A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier

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4 Author(s)
KwangSeok Kim ; Department of Electrical Engineering, KAIST, Daejeon, Korea ; Young-Hwa Kim ; Wonsik Yu ; SeongHwan Cho

In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate, and programmable gain for a wide input range. Using the proposed pulse-train time amplifier, a 7-bit two-step TDC is implemented. The proposed TDC employs repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. The prototype chip fabricated in 65 nm CMOS process achieves 3.75 ps of time resolution at 200 MS/s while consuming 3.6 mW and occupying 0.02 mm ^2 area. Compared to previously reported TDCs, the proposed TDC achieves the fastest conversion rate and the best FoM without any calibration.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:48 ,  Issue: 4 )