Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

On the Performance and Scaling of Symmetric Lateral Bipolar Transistors on SOI

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Ning, T.H. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Jin Cai

The performance potential and scaling characteristics of thin-base SOI symmetric lateral bipolar transistors were examined using 1-D analytic equations for the currents and capacitances. The device can operate at collector current densities >100 mA/μm2, and it scales similarly to CMOS in terms of density. The physical base width is scalable to less than 20 nm. Multiple devices of different specifications can be integrated on a chip. A sample design is shown to have fT > 200 GHz, fmax >1 THz, VA > 4V, and a self gain of 60. A balanced design is shown to have 350-GHz fT and 700-GHz fmax, VA of 2.4 V, and a self gain of 20. These results are superior to those reported for 32 nm SOI CMOS. The results suggest a need to rethink bipolar circuit design. They also suggest opportunities for novel bipolar and BiCMOS circuits. The devices in high-speed Si-base bipolar circuits operate at about 1.0 V. The path toward 0.5 V bipolar circuits is to use semiconductors with smaller bandgap, such as Ge.

Published in:

Electron Devices Society, IEEE Journal of the  (Volume:1 ,  Issue: 1 )