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In recent years, leakage power dominates the dynamic power in nanoscale CMOS VLSI circuits. This research paper describes different leakage mechanisms that includes subthreshold and gate leakage current. A novel approach of reduction in leakage current is proposed which is primarily based on the conventional gate replacement technique. This approach is more effective in circuits with higher logic depth. A comparative analysis is performed between the conventional and modified gate replacement mechanisms. Using the modified technique, the overall leakage current and number of replacements are reduced by 13.5% and 33.5% respectively as compared to the conventional one.