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A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology

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6 Author(s)
Ono, N. ; Corp. R&D Center, Toshiba Corp., Kawasaki, Japan ; Motoyoshi, M. ; Takano, K. ; Katayama, K.
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A 113 GHz 176.4 mW transmitter and receiver chipset using 65 nm CMOS technology is presented. To achieve low power consumption, an amplitude shift keying modulation with a simple circuit is adopted for this chipset, and the transmitter does not have a power amplifier. The power consumptions of the transmitter and receiver are 65.5 and 110.9 mW, respectively. A 2.5 Gbps pseudorandom bit sequence is successfully transferred from the transmitter to the receiver by wireless propagation through a distance of 0.2 m with a bit error rate of less than 10-8. The transmitter has an output power of -0.05 dBm.

Published in:

Microwave Conference Proceedings (APMC), 2012 Asia-Pacific

Date of Conference:

4-7 Dec. 2012