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A 1V 18 dBm 60GHz power amplifier with 24dB gain in 65nm LP CMOS

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3 Author(s)
Linhui Chen ; Sch. of Inf. Sci. & Eng., Southeast Univ., Nanjing, China ; Lianming Li ; Tie Jun Cui

A 60 GHz 4-way power-combining power amplifier (PA) is realized in a 65nm LP CMOS. The PA consists of three common-source (CS) pseudo-differential stages, in which a capacitive neutralization is used to increase the reverse isolation and the maximum gain (Gmax). To achieve high gain within a small area, a new inter-stage impedance matching network is proposed, consisting of transformer, transmission line and shunt inductor. The PA exhibits a small-signal gain of about 24dB, with 3dB bandwidth of more than 10GHz. The saturated output power (Psat) is 18 dBm and 19 dBm with 1 V and 1.2 V supply voltage, respectively. The peak PA E is 13.2% and P1dB is 14.8 dBm. The PA occupies an area of 0.74mm2, including pads.

Published in:

Microwave Conference Proceedings (APMC), 2012 Asia-Pacific

Date of Conference:

4-7 Dec. 2012