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Highly efficient 24-GHz CMOS linear power amplifier with an adaptive bias circuit

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3 Author(s)
Hyunji Koo ; Dept. of Electr. Eng., KAIST, Daejeon, South Korea ; Bonhoon Koo ; Songcheol Hong

A 24 GHz Power amplifier (PA) with high efficiency designed in the 0.13-μm CMOS process is presented. The proposed adaptive-bias circuit is used to improve the efficiency. The quiescent power consumption is 79.2 mW, which is improved by 53.8mW, compared to that of the optimized fixed-biased (0.6V) PA. Power added efficiency (PAE) and output power (POUT) at a 1-dB-gain-compression-power (P1dB) is 15.6 % and 13.3 dBm, respectively. This result is improved as much as 4% and 1.2dB, compare to that of PA with fixed-bias of 0.6V.

Published in:

Microwave Conference Proceedings (APMC), 2012 Asia-Pacific

Date of Conference:

4-7 Dec. 2012

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