By Topic

A 27–34 GHz CMOS medium power amplifier with a flat power performance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chao-Hsiuan Tsay ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Jui-Chih Kao ; Kun-Yao Kao ; Kun-You Lin

This paper presents a 27-34 GHz medium power amplifier in 65-nm CMOS technology. The amplifier is designed to amplify the LO signals from the 30-GHz VCO in a 60-GHz sub-harmonic direct-conversion system. The proposed amplifier achieves a measured gain of higher than 22.8 dB from 27 to 34 GHz, and the gain deviation is within 1 dB. The measured results show a PAE up to 13% at 1-dB compression power (P1dB), and a 7.7-dBm P1dB at 30 GHz. The peak PAE and the saturation power (Psat) are 23.3% and 10.6 dBm at 30 GHz, respectively. The P1dB is between 6.8 and 7.7 dBm while the Psat is between 9.7 and 10.8 dBm from 27 to 34 GHz. The chip size is 0.36 mm2 including all testing pads.

Published in:

Microwave Conference Proceedings (APMC), 2012 Asia-Pacific

Date of Conference:

4-7 Dec. 2012