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Highly digital-oriented architectures for sensor interfaces are very interesting for their high energy efficiency, especially in smaller CMOS technologies which offer low-voltage design. This paper presents the analysis of a Bang-Bang Phase-Locked Loop Sensor-to-Digital Converter (BBPLL SDC). The highly digital-oriented BBPLL offers advantages such as the low chip area, excellent scalability towards smaller technologies, robustness towards process variations and low-voltage possibilities, making this architecture very interesting for energy-efficient applications. Theoretical analysis of the structure shows that the BBPLL SDC resembles a -modulator with first-order quantization noise shaping due to the frequency-to-phase conversion of the oscillators. Oscillator phase noise however plays an important role in the analysis and limits the SNR in practical implementations. To validate the theoretical analysis, a state-variable-based non-linear Matlab model has been developed, including non-idealities such as phase noise, non-linearity and mismatch. Based on practically achievable phase noise values of state of the art oscillators, simulations show that resolutions up to 110 dB can be achieved. An estimation of the power consumption of the oscillators, based on state of the art figures, results in energy-efficient designs beyond the state of the art with moderate resolutions of 40-80 dB SNR, while high resolutions of 80-110 dB demand higher power consumption in the oscillators, resulting in designs with lower energy efficiency, but still competitive with the current state of the art. A design strategy for both an energy-efficient and a high-performance BBPLL SDC is provided.