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Due to increase in Vt (threshold voltage) variation caused by global and local process variations in ultrashort-channel devices, CMOS-based 6T SRAM cell and its variants cannot be operated at voltage lower than 600 mV. Therefore, this paper presents a FinFET-based 8T SRAM cell to mitigate impact of process variation. In this work, various design metrics are assessed and compared with MOSFET-based RD8T SRAM cell. The proposed design offers 4.35× and 1.86× improvements in TRA (read access time) and TWA (write access time) respectively compared to RD8T. It proves its robustness against process variations by featuring narrower spread in TRA distribution (6.95×) and TWA distribution (5.04×) compared with RD8T. These improvements are achieved at the expense of 11.65× higher read power and 13.75× higher write power. However, proposed bitcell exhibits 3.64× narrower spread in read power and 1.94× narrower spread in write power. Our bitcell achieves 6% improvement in RSNM compared with RD8T at the cost of reduction in WSNM (write static noise margin). However, it is still RSNM limited and is more balanced in terms of RSNM and WSNM.