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All-digital PLL with ΔΣ DLL embedded TDC

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7 Author(s)
Han, Y. ; Inst. of Microelectron., Tsinghua Univ., Beijing, China ; Lin, D. ; Geng, S. ; Xu, N.
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An all-digital PLL (ADPLL) which employs a ΔΣ delay-locked loop (DLL) to achieve a PVT-insensitive time resolution of the time-to-digital converter (TDC) as well as noise-shaped dithering is implemented in 65 nm CMOS. Experimental results show that the proposed method can achieve spur reduction with slight degradation of in-band phase noise. The 1.8 GHz ADPLL consumes 14.3 mW, while the TDC with the ΔΣ DLL consumes 2.1 mW.

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Electronics Letters  (Volume:49 ,  Issue: 2 )