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An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing

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5 Author(s)
Jendernalik, W. ; Fac. of Electron., Telecommun. & Inf., Gdansk Univ. of Technol., Gdansk, Poland ; Blakiewicz, G. ; Jakusz, J. ; Szczepanski, S.
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A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3 × 3 kernel. The proof-of-concept circuit is implemented in 0.35 μm CMOS technology, and contains a 64 × 64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 W per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:60 ,  Issue: 2 )