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A high-pass-filtered (HPF) pulse injection technique is proposed to reduce spurs near the carrier signal due to injection locking. By using this technique, a multi-band quadrature clock generator consisting of a wide-frequency range injection-locked PLL and a frequency-selectable local buffer is demonstrated. The proposed clock generator was fabricated in a 65 nm CMOS. For a 100 MHz reference, the circuit can output 1.0, 2.0, and 4.0 GHz quadrature outputs with an eight-phase VCO and the buffer. It shows an 1 MHz-offset phase noise -105 dBc/Hz and a reference spur level of -50 dBc at 2.0 GHz, with enabling HPF pulse injection. The total power consumption is lower than 32 mW at 4 GHz.