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A new parallel algorithm for time-slot assignment in hierarchical switching systems

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1 Author(s)
Chalasani, S. ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

The time-slot assignment (TSA) problem in a TDM switching system is to find a conflict-free assignment of traffic-units to slots such that the frame-length is minimized. In this paper, we develop a new parallel algorithm for the TSA problem in hierarchical switching systems (HSS). To design the parallel algorithm, we first reduce the TSA problem to the problem of routing permutations in three-stage Clos networks; we also show how this reduction can be achieved in polylogarithmic time using a polynomial number of processors on the EREW PRAM model. Once this reduction is achieved, we use existing parallel algorithms in literature to route permutations in Clos networks. The overall time-complexity of our parallel algorithm is O(log3 X) using O(MX) processors, where X=max{M, L}, M is the number of inputs of the HSS, and L is the length of the time-slot assignment. This result is a significant improvement upon the earlier parallel algorithms, which require O(M2 log M log L) time and O(ML) processors to solve the TSA problem

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Computers, IEEE Transactions on  (Volume:46 ,  Issue: 12 )