By Topic

A robust multithreaded HDL/ESL simulator for deep submicron integrated circuit designs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Chan, T. ; Dynetix Design Solutions Inc., Dublin, CA, USA

This paper describes a robust multithreaded Hardware Description Language (HDL) and Electronic System-Level (ESL) logic simulator, V2Sim™. The simulator uses patented [1] multithreaded simulation technology to achieve superior scalable performance on advanced multiprocessor/multicore computers. As further enhancements, we have incorporated a multithreaded race logic auditor and a multithreaded race logic synthesizer into V2Sim™, so that V2Sim™ can automatically detect race logic in user HDL/ESL designs, and fix those designs to eliminate race logic. This renders V2Sim™ can robustly handle any large-scale integrated circuit (IC) designs, and its multithreaded simulation results for those designs will be the same as that running on a single-CPU/core computer. Using V2Sim™, designers can cut-down their new IC product development time by 40% or more, and meet time-to-market.

Published in:

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Date of Conference:

2-5 Dec. 2012