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The reliability of non-volatile memory is a very important and critical issue for automotive embedded processors. In addition to the reliable cell as well as read and write circuitry design, the testing of endurance, burn-in, and run time safety design are all required in order to provide a reliable embedded non-volatile memory. In this paper, a novel architecture for the reliability test of non-volatile memory in embedded processor is proposed. The proposed approach especially meets the requirement for the reliability test of automotive electronics. Moreover, the extra hardware cost is minimized in the proposed methodology to cover all the testing requirements. By applying the proposed approach, the safety and memory space usage can be further optimized.