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Cache utilization-aware scheduling for multicore processors

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2 Author(s)
Chu, E.T.-H. ; Dept. of Comput. Sci. & Inf. Eng., Nat. Yunlin Univ. of Sci. & Technol., Yunlin, Taiwan ; Wen-wei Lu

A chip multiprocessor (CMP) consists of several cores which can execute tasks independently. Due to the budget and chip area limit, last level cache is usually shared among cores. If tasks running on different cores access the shared cache intensively and concurrently, it may lead to high cache miss rate and significant performance degradation. A commonly-used method is to co-schedule a task with good anti-interference ability and a task with poor anti-interference. However, if tasks have similar anti-interference abilities, it becomes difficult to generate a proper task assignment. In this paper, we identify two more indexes, intra-core cache contention and task interference ability, that primarily determine the utilization of shared cached. Based on the indexes, we develop a novel task scheduling, named cache utilization aware scheduling (CUAS), to reduce shared cache contention. CUAS first classifies tasks according to their anti-interference ability and interference ability. CUAS then distributes tasks to cores based on the effect of inter-core and intra-core cache contention. We conducted our experiments on an Intel Core2 Quad processor and adopted SPEC CPU2006 benchmark for evaluation. According to our experiment results, CUAS can significantly reduce shared cache contention and reduce total execution time at most 46% compared to existing methods.

Published in:

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Date of Conference:

2-5 Dec. 2012