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A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology

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4 Author(s)
Sheng-Hsiung Lin ; Dept. of EE, Nat. Cheng Kung Univ., Tainan, Taiwan ; Jin-Fu Lin ; Guan-Ying Huang ; Soon-Jyh Chang

This paper presents a 12-bit 50-MS/s pipelined SAR analog-to-digital converter (ADC) with loading-separating technique. The proposed loading-separating technique relaxes output loading of multiplying digital-to-analog converter (MDAC) and increases the time budget of bit cycling for the 2nd stage. In addition, a split-path amplification MDAC is proposed to enhance amplifier's gain and bandwidth. The ADC core occupies an active area of 0.27 mm2 in TSMC 90-nm 1P9M CMOS process. The measured results show that the proposed ADC achieves 63.56 dB SNDR with 2.17 mW power consumption.

Published in:

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Date of Conference:

2-5 Dec. 2012

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