Cart (Loading....) | Create Account
Close category search window
 

A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Sheng-Hsiung Lin ; Dept. of EE, Nat. Cheng Kung Univ., Tainan, Taiwan ; Jin-Fu Lin ; Guan-Ying Huang ; Soon-Jyh Chang

This paper presents a 12-bit 50-MS/s pipelined SAR analog-to-digital converter (ADC) with loading-separating technique. The proposed loading-separating technique relaxes output loading of multiplying digital-to-analog converter (MDAC) and increases the time budget of bit cycling for the 2nd stage. In addition, a split-path amplification MDAC is proposed to enhance amplifier's gain and bandwidth. The ADC core occupies an active area of 0.27 mm2 in TSMC 90-nm 1P9M CMOS process. The measured results show that the proposed ADC achieves 63.56 dB SNDR with 2.17 mW power consumption.

Published in:

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Date of Conference:

2-5 Dec. 2012

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.