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A novel quantization algorithm suitable for high-speed analog-to-digital converters

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2 Author(s)
Soufizadeh-Balaneji, N. ; Electr. Eng. Dept., Urmia Univ., Urmia, Iran ; Hadidi, K.

A novel quantization algorithm capable of being employed in high-resolution high-speed ADCs is described. In order to verify the efficiency of proposed architecture a 3.3-V 10-bit ADC with roughly 67-dB spurious free dynamic range (SFDR) and 59-dB signal-to-noise-and-distortion ratio (SNDR) has been reported. The converter designed in standard 0.35-μm CMOS technology consumes 156 mW from a nominal supply voltage when it operates at a sampling rate of 80-Msample/s.

Published in:

Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on

Date of Conference:

2-5 Dec. 2012