Prototype trigger and readout-electronics built on unified Altera® platform for underground muon counters triggered by surface detectors

The paper describes the prototype of the Master/Slave (a water Cherenkov surface detector triggers the underground muon counters) synchronous data acquisition system with 80/320 MHz sampling in the surface/underground segments built on unified Altera
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platform - CycloneIII/CycloneIV
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FPGAs with implemented NIOS
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processors in each segment. NIOS
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processors eliminate external micro-controllers and allow generating necessary interfaces: SDRAM controller, UART, SPI, DMA, previously implemented from logic elements. Moving several slow tasks from the logic block (coding in the AHDL) to the NIOS
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(coding in C) dramatically simplifies the system and increases its flexibility. A time margin for all processes managing by the soft-core NIOS
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for the 100 Hz T1 trigger rate remains sufficient. Splitting 64 input channel just after fast input FPGA registers clocked by 320 MHz into 128-bit bus with twice lower clock allows achieving global registered performance of 160 MHz for the entire trigger/memory circuitry. NIOS
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processors communicate each other via UART protocol and RS485 standard. Underground CycloneIV
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FPGA is programmed remotely via additional MAXII CPLD with non-volatile programming memory. Tests have showed that a full synchronous cycle: a transfer of the trigger with a time stamp from the surface detector into the underground segment via a dedicated line with a galvanic barrier, freezing data from 64 channels at 320 MHz sampling in an internal DPRAMs, writing/reading data into/from external SDRAM, extraction physical data identified by sent from Central Data Acquisition System (CDAS) GPS time stamps and its transfer from the underground NIOS
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via surface NIOS
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to CDAS, is successful.