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Wafer-level 3-D integration using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn-BCB hybrid bonding is investigated with electrical leakage current. With the well-fabricated Cu TSVs and Cu/Sn bond structures, the leakage current path in this scheme due to backside process was found, and the corresponding mechanism is discussed. The leakage current can be solved by the modified backside process. The improved 3-D integration scheme shows extremely low leakage current and no visible defects inside Cu TSV.