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From the point of view of the industry, floorplanning is very important in VLSI chip physical design because it will deeply affect the time-to-market and the quality of the product. A new floorplanning algorithm namely Pre-Post Terminal Propagation (PPTP) has been proposed to handle soft module floorplanning by employing multilevel framework. Pre-Terminal Propagation is employed at the root node only in order to increase more possible partitionings, as introduction of TP at every level will restrict the partitioning results. However, non-inclusion of TP at the subsequent partitioning will lead to the lack of information about the external pins at every level in the tree. Hence, Post-Terminal Propagation is adapted to compensate this deficiency. PPTP gives improved optimal HPWL solutions and faster runtimes for soft module floorplanning based on Gigascale Systems Research Center (GSRC) benchmarks. The results obtained establish that PPTP is a high performance floorplanner as compared to other state-of-the-art floorplanning algorithms. This indicates this makes PPTP more suitable for industrial VLSI physical design implementation.