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High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using \hbox {HfO}_{2}/\hbox {Al}_{2}\hbox {O}_{3}/\hbox {GeO}_{x}/\hbox {Ge} Gate Stacks Fabricated by Plasma Postoxidation

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6 Author(s)
Rui Zhang ; Sch. of Eng., Univ. of Tokyo, Tokyo, Japan ; Po-Chin Huang ; Ju-Chin Lin ; Taoka, N.
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An ultrathin equivalent oxide thickness (EOT) HfO2/Al2O3/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al2O3 layer between HfO2 and Ge for suppressing HfO2-GeOx intermixing, resulting in a low-interface-state-density (Dit) GeOx/Ge metal-oxide-semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7-0.8 nm with maintaining the Dit in 1011 cm-2·eV-1 level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 cm2/V·s and peak electron mobilities of 754 and 689 cm2/V·s at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present HfO2/Al2O3/GeOx/Ge gate stacks.

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Electron Devices, IEEE Transactions on  (Volume:60 ,  Issue: 3 )