Cart (Loading....) | Create Account
Close category search window
 

A four-level storage 4-Gb DRAM

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Okuda, T. ; ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan ; Murotani, T.

A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each corresponding to two-bit-data storage in a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier using charge coupling and charge sharing was developed for the four-level sensing and restoring. The sense amplifier uses a hierarchical bit-line scheme and operates in a time-sharing mode, thus reducing the sense amplifier area. A 4-Gb DRAM fabricated using 0.15-μm CMOS technology measures 986 mm2. The memory cell is 0.23 μm2. Its capacitance of 60 fF is achieved by using a high-dielectric-constant material BST

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:32 ,  Issue: 11 )

Date of Publication:

Nov 1997

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.