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A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme

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4 Author(s)
M. Tsukude ; Memory IC Div., Mitsubishi Electr. Corp., Hyogo, Japan ; S. Kuge ; T. Fujino ; K. Arimoto

A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 Vcc bit-line precharge achieves a five times larger readout voltage and 40% improvement in sensing speed compared with conventional sensing schemes. Operation over a 1.2- to 3.3-V range is achieved. A nonreset row block control scheme (NRBC) for power-consumption improvement in data-retention mode is proposed which decreases the charge/discharge number of the row block control circuit. By combining CTPS and NRBC, the data-retention current is reduced by 75%

Published in:

IEEE Journal of Solid-State Circuits  (Volume:32 ,  Issue: 11 )