By Topic

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Tsukude, M. ; Memory IC Div., Mitsubishi Electr. Corp., Hyogo, Japan ; Kuge, S. ; Fujino, T. ; Arimoto, K.

A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 Vcc bit-line precharge achieves a five times larger readout voltage and 40% improvement in sensing speed compared with conventional sensing schemes. Operation over a 1.2- to 3.3-V range is achieved. A nonreset row block control scheme (NRBC) for power-consumption improvement in data-retention mode is proposed which decreases the charge/discharge number of the row block control circuit. By combining CTPS and NRBC, the data-retention current is reduced by 75%

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:32 ,  Issue: 11 )