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A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller

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13 Author(s)
G. Gerosa ; Somerset Design Center, Austin, TX, USA ; M. Alexander ; J. Alvarez ; C. Croxton
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This RISC microprocessor is a new, high-performance, PowerPC microprocessor designed specifically for the mobile and high volume desktop personal computer markets. It is an advanced superscalar design with six execution units, aggressive upstream branch processing, out-of-order instruction execution, and a tightly integrated “backside” L2 cache. This dual-issue engine has a four-stage pipeline with dual 32-kB eight-way set-associative L1 caches and an integrated L2 controller with on-chip L2 tag supporting up to 1 MB of external SRAM. A thermal assist unit and an instruction cache throttling mechanism are included for thermal management in mobile applications. A 60X system bus and L2 interface speeds of 100 and 250 MHz are achieved, respectively. This microprocessor achieves workstation class performance (estimated 10 SPECint95 and 9 SPECfp95) while only dissipating 5 W at 250 MHz. The 6.35-million transistor 66.5-mm2 die is fabricated in a 2.5-V, 0.3-μm, five-layer metal CMOS process

Published in:

IEEE Journal of Solid-State Circuits  (Volume:32 ,  Issue: 11 )