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Fault mitigation by means of dynamic partial reconfiguration of Virtex-5 FPGAs

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3 Author(s)
Andres Upegui ; InIT Institute - hepia, University of Applied Sciences of Western Switzerland, Geneva, Switzerland ; Julien Izui ; Gilles Curchod

This paper presents a technique to mitigated SEU faults on Virtex-5 FPGAs through the use of dynamic partial reconfiguration. The key idea is to reconfigure the damaged part of the configuration bitstream in order to repair the bitstream and, thus, the overlying architecture. To this end, we propose a design flow and a set of tools that allow us to manipulate the bitstream generation. As case study, we present an application using an AES encryption coprocessor, a fault detection system constantly verifying system integrity and repairing faults, and an independent program injecting faults to validate the system.

Published in:

2012 International Conference on Reconfigurable Computing and FPGAs

Date of Conference:

5-7 Dec. 2012