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Increasing complexity of integrated circuits has forced the industry to abandon partial scan, which necessitates a computationally demanding and unaffordable sequential automatic test pattern generation (ATPG), and to instead adopt full scan, despite its costs. In this paper, we propose a partial scan scheme driven by a computationally efficient test cube analysis. We tackle the challenges associated with the identification of the conditions to restore the controllability and observability compromised due to partial scan, and with the formulation of these conditions in terms of test cube operations. Upon the identification of a maximal-sized set of scan flip-flops that are converted to nonscan, a simple postprocessing of the test cubes helps compute the values to be loaded into the scan flip-flops, eliminating the need to rerun ATPG, while at the same time ensuring the quality of full scan. We further enhance this framework through techniques that process the test data before and after the application of the proposed test cube analysis-driven partial scan technique, in order to enlarge the size of the nonscan flip-flop set. The proposed scheme combines the simplicity of the conventional ATPG flow with the area, performance, test time, and test power reduction benefits of partial scan. The proposed test cube analysis-driven partial scan scheme is orthogonal and thus fully compatible with other test cost-reduction techniques, such as test data compression and test power reduction, which can be applied in conjunction.