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This Special Section considers several studies that emphasize cross-domain physical optimization. The first paper applies physical optimization techniques that cut across the discrete and continuous domains; a geometric programming method is applied to solve the classical floorplanning problem. The second paper introduces a subfield scheduling approach that considers both ebeam lithography throughput and the thermal effect in the ebeam writing process. The third paper presents techniques that make the circuit layout compatible with multiple-patterning lithography. The fourth paper describes an integrated design methodology for microfluidic chips that encompasses operation scheduling, chip layout generation, control pin assignment, and wiring solution. The fifth paper crosses the boundaries of datapath design and random logic; it proposes a placement flow that simultaneously places a mixture of random logic and datapath cells found in hybrid designs. The short paper replaces flipflops with pulsed latches, and utilizes the time-borrowing property of pulsed latches and clock gating to achieve power efficiency.