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A Dual-Junction Single-Photon Avalanche Diode in 130-nm CMOS Technology

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3 Author(s)
Robert K. Henderson ; Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, Edinburgh, U.K. ; Eric A. G. Webster ; Lindsay A. Grant

A dual-junction single-photon avalanche diode structure is reported in a 130-nm low-voltage CMOS technology. The device comprises two stacked avalanche multiplication regions with virtual guard ring constructions. An 8.6- μm-diameter p-well is placed within a 12.3- μm-diameter deep n-well. At 3-V excess bias, the junctions operate with median dark count rates of 10 and 5 kHz and photon detection efficiencies of 32% at 450 nm and 29% at 670 nm, respectively. We demonstrate that the junction at which a photon is detected can be uniquely distinguished by the dead time of the Geiger mode pulse allowing spectral discrimination by simple digital circuitry.

Published in:

IEEE Electron Device Letters  (Volume:34 ,  Issue: 3 )