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Reliable Ultra-Low-Voltage Cache Design for Many-Core Systems

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3 Author(s)
Meilin Zhang ; University of Rochester, NY ; Vladimir M. Stojanovic ; Paul Ampadu

We reduce cache supply voltage below the normally acceptable VDDMIN, in order to improve overall many-core system energy efficiency. Based on the observation that cache lines contain mostly one hard faulty cell at these ultra-low supply voltages, we exploit existing double-error correcting triple-error detecting codes, together with cache line disabling, to handle both soft and hard cache faults, thus enabling reliable ultra-low supply voltage cache operation. Compared to the next-best approach in the research literature, the proposed method reduces system energy consumption by up to 25% and energy-execution time product by nearly 10%, while introducing only 0.28% storage overhead and marginal instruction per cycle degradation, when the target yield loss rate is 1/1000.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:59 ,  Issue: 12 )