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Recently, IEEE802.11ac, which can support ultra high speed data communications up to 1Gbps with low power consumption, has been drawing much attention in the consumer electronic field. In the IEEE802.11ac system, one of the critical implementation issues is to find the optimum architecture of demodulator satisfying the speed requirement. A Viterbi decoder is an essential part for error correction in the demodulator and has a design problem with respect to hardware costs as well as decoding speed. Among various functional blocks in the Viterbi decoder, both hardware complexity and decoding speed highly depend on the architecture of ACS. Because of a feed-back structure, it is very difficult for the ACS to perform its task at a high data rate at low power. Substantial previous works have been presented in order to enhance the decoding speed or to reduce the hardware costs. However, the approaches are insufficient to meet the high-speed and low-cost requirements of a high-level soft decision (up to 8 bits) Viterbi decoder for IEEE802.11ac systems. In this paper, therefore, we propose a cost-efficient high-level soft decision Viterbi decoder with a multi-stage pipelined ACS for IEEE802.11ac systems. From the implementation and verification results under 0.13μm CMOS technology, we find that the proposed architecture can meet the required data rate of IEEE802.11ac and reduce the hardware complexity by about 70% and 90% compared with conventional single-stage pipelined ACS and look-ahead ACS structures, respectively.