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Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through

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1 Author(s)
Jin-Fa Lin ; Dept. of Inf. & Commun. Eng., Chaoyang Univ. of Technol., Taichung, Taiwan

In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and power- delay-product metrics are 22.7% and 29.7%, respectively.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:22 ,  Issue: 1 )