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Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array

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3 Author(s)
Stillmaker, A. ; Electr. & Comput. Eng. Dept., Univ. of California, Davis, Davis, CA, USA ; Stillmaker, L. ; Baas, B.

Data centers require significant and growing amounts of power to operate, and with increasing numbers of data centers worldwide, power consumption for enterprise workloads is a significant concern. Sorting is a key computational kernel in large database systems, and the development of energy efficient sorting capabilities would therefore significantly reduce data center power usage. We propose highly parallel sorting algorithms and mappings using a modular design for a fine-grained many-core system that greatly decreases the amount of energy consumed to perform sorts of arbitrarily large data sets. The memory, computational, and nearest-neighbor inter-processor communication hardware of the many-core processor array require relatively small die area. We present the design and implementation of several sorting variants that perform the first phase of an external sort. They are built using program kernels operating on independent processors in a many-core array with 256 bytes of data memory and fewer than 128 instructions per processor. The algorithms employed are simple and the vast majority of processors contain identical programs. Compared to a quicksort implementation on an Intel Core 2 Duo T9600 the highest throughput design achieves up to 27× higher throughput per chip area, and the most energy efficient sort yields a 330× reduction in energy dissipated per sorted block. Compared to a radix sort implementation on a GPU, the highest throughput design achieves up to 22× higher throughput per chip area, and the most energy efficient sort yields a 750× reduction in energy dissipated per sorted block.

Published in:

Parallel and Distributed Systems (ICPADS), 2012 IEEE 18th International Conference on

Date of Conference:

17-19 Dec. 2012