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A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface System

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7 Author(s)
Sunkwon Kim ; Dept. of Electr. Eng., Seoul Nat. Univ., Seoul, South Korea ; Jong-Kwan Woo ; Woo-Yeol Shin ; Gi-Moon Hong
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We propose a low-voltage low-power clock and data recovery (CDR) circuit which incorporates a relaxation-based voltage-controlled oscillator and clock-edge modulation, which eliminates the need for an external reference clock without allowing harmonic locking. This CDR supports input data rates between 200 kbps and 10 Mbps at 0.7 V and operates up to 24 MHz at 1.0 V. The proposed design consumes 8 at an input data rate of 10 Mbps and achieves 0.8 pJ/bit of energy per bit even though the circuit is implemented in a 0.18- μm CMOS technology.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:60 ,  Issue: 1 )

Date of Publication:

Jan. 2013

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