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Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub- V_{ \rm T} Operation

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2 Author(s)
Winstead, C. ; Dept. of Electr. & Comput. Eng., Utah State Univ., Logan, UT, USA ; Rodrigues, J.N.

Techniques are evaluated for implementing error correction codes in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-VT analog decoding techniques. Novel sub-VT digital designs are proposed, and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub-VT implementation is predicted to offer 29× gain in power consumption for a (3,6) low-density parity-check decoder of length N = 512 operating at a throughput of 200 Mb/s, compared to standard digital implementation of the same design.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 12 )

Date of Publication:

Dec. 2012

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