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Stability Analysis of Bang-Bang Phase-Locked Loops for Clock and Data Recovery Systems

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1 Author(s)
Jae-Yong Ihm ; Syst. LSI Bus., Samsung Electron. Co., Ltd., Yongin, South Korea

Bang-bang phase detector-based phase-locked loops (PLLs) with first- and second-order analog loop filters (LFs) are considered. Discrete-time (DT) models are presented for the bang-bang PLLs (BPLLs) in the presence of loop delays. The DT models show that the delay introduces an additional pole at in the DT open-loop transfer function. The pole is of multiple order proportional to the delay, indicating that the system is prone to be unstable. Stability analysis of the BPLLs is conducted to derive stability conditions, taking advantage of the radius of curvature technique to facilitate numerical calculations involved. It is shown that the stability conditions depend on the LF parameters, the loop delay, and the update time of the BPLLs.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:60 ,  Issue: 1 )