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FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm

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2 Author(s)
Kasap, S. ; Dept. of Electr. & Electron. Eng., Eur. Univ. of Lefke, Gemikonagi, Cyprus ; Redif, S.

In this paper, we introduce a field-programmable gate array (FPGA) hardware architecture for the realization of an algorithm for computing the eigenvalue decomposition (EVD) of para-Hermitian polynomial matrices. Specifically, we develop a parallelized version of the second-order sequential best rotation (SBR2) algorithm for polynomial matrix EVD (PEVD). The proposed algorithm is an extension of the parallel Jacobi method to para-Hermitian polynomial matrices, as such it is the first architecture devoted to PEVD. Hardware implementation of the algorithm is achieved via a highly pipelined, non-systolic FPGA architecture. The proposed architecture is scalable in terms of the size of the input para-Hermitian matrix. We demonstrate the decomposition accuracy of the architecture through FPGA-in-the-loop hardware co-simulations. Results confirm that the proposed solution gives low execution times while reducing the number of resources required from the FPGA.

Published in:

Field-Programmable Technology (FPT), 2012 International Conference on

Date of Conference:

10-12 Dec. 2012