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Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs

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4 Author(s)
Chao Wang ; Dept. of Comput. Sci., Univ. of Sci. & Technol. of China, Suzhou, China ; Xi Li ; Xuehai Zhou ; Yajun Ha

Reconfigurable hybrid multi-processor systems-on-chips (MPSoCs) are very powerful computing platforms. However, it has been quite challenging to schedule and map tasks to different function units of the MPSoCs, especially for tasks with inter-task dependencies. This paper introduces a parallel dataflow execution support, called ReArc, for the FPGA based reconfigurable hybrid MPSoCs. It constructs a hierarchical model for the high level programming with a parallel execution flow and dynamic reconfigurations. A prototype has been built on a Xilinx FPGA with a state-of-the-art software-hardware co-design paradigm. Experimental results demonstrate that ReArc could significantly facilitate researchers to construct a high-level, application oriented FPGA implementation with acceptable hardware utilizations and reconfiguration overheads.

Published in:

Field-Programmable Technology (FPT), 2012 International Conference on

Date of Conference:

10-12 Dec. 2012