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We propose a neural network based approach for estimating the total wirelength of a digital circuit, mapped onto an FPGA, before circuit placement and routing. A 3-layer MLP neural network is trained to learn the behavior of a placement tool and then quickly predicts the wirelength of a circuit design with the accuracy similar to one obtained after placement. A priori knowledge about the wirelength of circuit designs can be used to effectively guide the design exploration processes at the early design stages. This breaks the repetitive CAD design flow and reduces the design cycle. In this work, five circuit parameters and two FPGA architecture parameters are considered in the wirelength estimation. The proposed approach is evaluated by comparing the wirelength given by the trained neural networks and the placement tool VPR for the IWLS2005 circuit benchmark. Results show that the neural network's estimation has an average error below 0.6% compared to VPR. The neural network model is also compared to a linear model for the wirelength estimation, showing 7.39 times improvement in the estimation accuracy.