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3-D Stacking of Ultrathin Chip Packages: An Innovative Packaging and Interconnection Technology

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4 Author(s)
Priyabadini, S. ; Dept. of Electron. & Inf. Syst., Ghent Univ., Ghent, Belgium ; Sterken, T. ; Van Hoorebeke, L. ; Vanfleteren, J.

In order to increase the functionality of electronic devices, while reducing the overall size and weight of the electronic chip packages, electronic chip packages can be combined into a 3-D assembly. In this field, we present a technology for stacking multiple chip packages, resulting in total volume almost equal to that of a single bare die. The technology is based on batch-processed ultrathin chip packages (UTCPs) with a fine pitch metal fan-out. Package-on-package technology enables stacking of UTCPs by vacuum lamination, followed by throughhole interconnection technology for making contacts to the metal fan-out of the embedded UTCPs within the stack. The individual chip packages can be tested before stacking.

Published in:

Components, Packaging and Manufacturing Technology, IEEE Transactions on  (Volume:3 ,  Issue: 7 )

Date of Publication:

July 2013

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