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Magnetic Adder Based on Racetrack Memory

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6 Author(s)
Hong-Phuc Trinh ; IEF, Univ. Paris-Sud, Orsay, France ; Weisheng Zhao ; Klein, J.-O. ; Yue Zhang
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The miniaturization of integrated circuits based on complementary metal oxide semiconductor (CMOS) technology meets a significant slowdown in this decade due to several technological and scientific difficulties. Spintronic devices such as magnetic tunnel junction (MTJ) nanopillar become one of the most promising candidates for the next generation of memory and logic chips thanks to their non-volatility, infinite endurance, and high density. A magnetic processor based on spintronic devices is then expected to overcome the issue of increasing standby power due to leakage currents and high dynamic power dedicated to data moving. For the purpose of fabricating such a non-volatile magnetic processor, a new design of multi-bit magnetic adder (MA)-the basic element of arithmetic/logic unit for any processor-whose input and output data are stored in perpendicular magnetic anisotropy (PMA) domain wall (DW) racetrack memory (RM)-is presented in this paper. The proposed multi-bit MA circuit promises nearly zero standby power, instant ON/OFF capability, and smaller die area. By using an accurate racetrack memory spice model, we validated this design and simulated its performance such as speed, power and area, etc.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:60 ,  Issue: 6 )