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The growing market of portable electronic devices demands lesser power dissipation for longer battery life and compact system. Advancement of tech nology effectively minimizes the leakage current & power and size of cell. Leakage current in cell is the dominating factor, which is greatly affects the power consumption. Optimization of power and delay is very important issue in low voltage and low power applications. This paper is a case study for designing of high speed, compact and power efficient half adder circuit. In this work the impact of leakage on Half Adder is described and two approaches are used for reducing leakage current in active mode. In one approach the supply voltage is scaled down and in other approach leakage is minimized by technology scaling from 180nm to 45nm CMOS technology. The Half Adder design simulation work was performed by Cadence simulation tool in 45 & 180 nm Technology at 27°C with supply voltage variation.