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Exploiting SPM-aware Scheduling on EPIC architectures for high-performance real-time systems

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2 Author(s)
Yu Liu ; Dept. of ECE, Virginia Commonwealth Univ., Richmond, VA, USA ; Wei Zhang

In contemporary computer architectures, the Explicitly Parallel Instruction Computing Architectures (EPIC) permits microprocessors to implement Instruction Level Parallelism (ILP) by using the compiler, rather than complex on-die circuitry to control parallel instruction execution like the superscalar architecture. Based on the EPIC, this paper proposes a time predictable two-level scratchpad based memory architecture, and a Scratchpad-aware Scheduling method to improve the performance by optimizing the Load-To-Use Distance.

Published in:

High Performance Extreme Computing (HPEC), 2012 IEEE Conference on

Date of Conference:

10-12 Sept. 2012