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A low-power high-gain 2.45-GHz CMOS dual-stage LNA with linearity enhancement

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6 Author(s)
Eshghabadi, F. ; Sch. of Electr. & Electron. Eng., Univ. Sains Malaysia, Nibong Tebal, Malaysia ; Eshghabadi, H.A. ; Noh, N.M. ; Mustaffa, M.T.
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This paper presents a dual-stage LNA design which is enhanced for gain, linearity and noise figure under a certain power constraint. The LNA benefits from an inductively-degenerated cascode amplifier in the first stage which is followed by a common-source amplifier as the second stage. Two techniques are used to improve the linearity of this 24-dB gain LNA while maintaining the noise figure equal to 2 dB. An input 1-dB gain compression point of -21 dBm was achieved at 2.45-GHz operating frequency. The 0.13-μm CMOS LNA draws a 4-mA current from a 1.2-volt power supply.

Published in:

Circuits and Systems (ICCAS), 2012 IEEE International Conference on

Date of Conference:

3-4 Oct. 2012

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